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This section describes the state machine implementation strategies and coding aspects for hierarchical state machines in c and c++ For those who don't know, a hierarchical state machine is basically a reorganization of the finite state machine so that each state becomes, in effect, its own fsm (though with the important exception that transitions are allowed to cross hierarchical levels so technically each inner fsm is not closed under transition and thus not a true f. Class toastoven with a hierarchical state machine used in the following examples of code generation
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Statesmith is a cross platform, free/open source tool for generating state machines in multiple programming languages A state machine that supports hierarchy is known as a hierarchical state machine (hsm). The generated code is human readable, has zero dependencies and is suitable for use with tiny bare metal microcontrollers, video games, apps, web, computers.
When the model meets the design requirements, you then generate vhdl ®, verilog ® or systemverilog code that implements the design
The state machine is defined using a basic json string, and includes convenience timers. Logicblocks provides a source generator that can generate uml state diagrams of your code Generated uml diagrams are placed alongside the code for your logic block with the *.g.puml extension You can use plantuml (and/or the plantuml vscode extension) to visualize the generated diagram code.
Frame supports the notion of states inheriting behavior from other states
